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RTL Design using Verilog

Department of Electrical & Electronics Engineering in Association with IEEE has inaugurated the Blended Learning Course on “RTL Design using Verilog” on 11.08.2016, with M.S.Damodara, Product Manager, Global IEEEand the classes commenced from 11.08.2016.


RTL Verification using Verilog:
  • Exposes the learner to the techniques used in the industry to identify and fix design bugs that creep in while designing large VLSI IC’s using Verilog.
  • At the end of this course the learner will be able to describe what RTL verification is and why it is required. .
  • The learner will be able to develop a verification plan from the design specifications, develop test benches for the same in Verilog and debug designs using an industry standard RTL simulator.
  • Training in the application of concepts through extensive trainer-led concept labs, followed by project work
  • Course Completion Certificate under the banner of IEEE.
Duration of the Course::

50 Hours

Convenor: :

Dr.S.Kalyani,Ph.D., HoD/EEE

Course Coordinator::

M.Sudalaimani, M.E., Asst.Prof/EEE